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Integrated Circuit Systems, Inc.
ICS8745B
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
FEATURES
* 5 differential LVDS outputs designed to meet or exceed the requirements of ANSI TIA/EIA-644 * Selectable differential clock inputs * CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL * Output frequency range: 31.25MHz to 700MHz * Input frequency range: 31.25MHz to 700MHz * VCO range: 250MHz to 700MHz * External feedback for "zero delay" clock regeneration with configurable frequencies * Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 * Cycle-to-cycle jitter: 30ps (maximum) * Output skew: 35ps (maximum) * Static phase offset: 25ps 125ps * 3.3V supply voltage * 0C to 70C ambient operating temperature * Lead-Free package fully RoHS compliant
GENERAL DESCRIPTION
The ICS8745B is a highly versatile 1:5 LVDS Clock Generator and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8745B has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 31.25MHz to 700MHz. The Reference Divider, Feedback Divider and Output Divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve "zero delay" between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.
ICS
BLOCK DIAGRAM
PLL_SEL /1, /2, /4, /8, /16, /32, /64 0 1 CLK1 nCLK1 CLK_SEL FB_IN nFB_IN 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 1 0
PIN ASSIGNMENT
Q0 nQ0
VDD PLL_SEL SEL3 GND VDDO VDDA nQ4
Q1 nQ1 Q2 nQ2 Q3 nQ3
Q4
CLK0 nCLK0
32 31 30 29 28 27 26 25 SEL0 SEL1 CLK0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VDD nFB_IN FB_IN SEL2 GND nQ0 Q0 VDDO
24 23 22
Q3 nQ3 VDDO Q2 nQ2 GND Q1 nQ1
PLL
Q4 nQ4
nCLK0 CLK1 nCLK1 CLK_SEL MR
ICS8745B
21 20 19 18 17
SEL0 SEL1 SEL2 SEL3 MR
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
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REV. B DECEMBER 2, 2004
8745BY
Integrated Circuit Systems, Inc.
ICS8745B
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Type Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6 7 Name SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL Input Input Input Input Input Input Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Pullup Inver ting differential clock input. Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Clock select input. When HIGH, selects CLK1, nCLK1. Pulldown When LOW, selects CLK0, nCLK0. LVCMOS / LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx to go Pulldown high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Core supply pins. Pullup Feedback input to phase detector for regenerating clocks with "zero delay". Pulldown Feedback input to phase detector for regenerating clocks with "zero delay". Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. Power supply ground. Differential output pair. LVDS interface levels. Output supply pins. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. Analog supply pin. Selects between the PLL and reference clock as the input to the dividers. When LOW, selects reference clock. LVCMOS / LVTTL interface levels.
8 9, 32 10 11 12 13, 19, 25 14, 15 16, 22, 28 17, 18 20, 21 23, 24 26, 27 29 30 31
MR VDD nFB_IN FB_IN SEL2 GND nQ0, Q0 VDDO nQ1, Q1 nQ2, Q2 nQ3, Q3 nQ4, Q4 SEL3 VDDA PLL_SEL
Input Power Input Input Input Power Output Power Output Output Output Output Input Power Input
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
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REV. B DECEMBER 2, 2004
Integrated Circuit Systems, Inc.
ICS8745B
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Outputs PLL_SEL = 1 PLL Enable Mode Q0:Q4, nQ0:nQ4 /1 /1 /1 /1 /2 /2 /2 /4 /4 /8 x2 x2 x2 x4 x4 x8
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs SEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reference Frequency Range (MHz)* 250 - 700 125 - 350 62.5 - 175 31.25 - 87.5 250 - 700 125 - 350 62.5 - 175 250 -700 125 - 350 250 - 700 125 - 350 62.5 - 175 31.25 - 87.5 62.5 - 175 31.25 - 87.5 31.25 - 87.5
*NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz.
TABLE 3B. PLL BYPASS FUNCTION TABLE
Inputs SEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
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SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Outputs PLL_SEL = 0 PLL Bypass Mode Q0:Q4, nQ0:nQ4 /4 /4 /4 /8 /8 /8 / 16 / 16 / 32 / 64 /2 /2 /4 /1 /2 /1
REV. B DECEMBER 2, 2004
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Integrated Circuit Systems, Inc.
ICS8745B
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
4.6V -0.5V to VDD + 0.5V 10mA 15mA 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 125 17 59 Units V V V mA mA mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter VIH VIL IIH Input High Voltage Input Low Voltage Input High Current CLK_SEL, MR, SEL0, SEL1, SEL2, SEL3 PLL_SEL CLK_SEL, MR, SEL0, SEL1, SEL2, SEL3 PLL_SEL VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 150 5 Units V V A A A A
IIL
Input Low Current
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter IIH IIL VPP VCMR Input High Current Input Low Current CLK0, CLK1, FB_IN nCLK0, nCLK1, nFB_IN CLK0, CLK1, FB_IN nCLK0, nCLK1, nFB_IN Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 0.15 GND + 0.5 1.3 VDD - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2
NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VDD + 0.3V.
8745BY
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REV. B DECEMBER 2, 2004
Integrated Circuit Systems, Inc.
ICS8745B
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Test Conditions Minimum 320 1.05 Typical 440 0 1.2 Maximum 550 50 1.35 25 Units mV mV V mV
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol fIN Parameter Input Frequency CLK0, nCLK0, CLK1, nCLK1 Test Conditions PLL_SEL = 1 PLL_SEL = 0 Minimum 31.25 Typical Maximum 700 700 Units MHz MHz
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Static Phase Offset; NOTE 2, 5 Output Skew; NOTE 3, 5 Cycle-to-Cycle Jitter ; NOTE 5, 6 Phase Jitter ; NOTE 4, 5, 6 Output Duty Cycle PLL Lock Time 46 50 PLL_SEL = 0V, f 700MHz PLL_SEL = 3.3V 3.1 -100 3. 4 25 Test Conditions Minimum Typical Maximum 700 3. 7 150 35 30 52 54 1 70 0 Units MHz ns ps ps ps ps % ms ps
tsk(O) tsk(o) tjit(cc) tjit()
odc tL
tR / tF Output Rise/Fall Time; NOTE 7 200 NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal across all conditions, when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Characterized at VCO frequency of 622MHz. NOTE 7: Measured from the 20% to 80% points. Guaranteed by characterization. Not production tested.
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REV. B DECEMBER 2, 2004
Integrated Circuit Systems, Inc.
ICS8745B
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
3.3V
VDD
SCOPE
Qx
Power Supply +
Float GND
nCLK0, nCLK1
-
LVDS
nQx
V
CLK0, CLK1
PP
Cross Points
V
CMR
GND
3.3V OUTPUT LOAD AC TEST CIRCUIT
nCLK0, nCLK1 CLK0, CLK1 nFB_IN FB_IN
t(O)
DIFFERENTIAL INPUT LEVEL
VOH VOL VOH VOL
nQx Qx nQy Qy
tsk(o)
tjit(O) = t(O) -- t(O) mean = Phase Jitter t(O) mean = Static Phase Offset
(where t(O) is any random sample, and t(O) mean is the average of the sampled cycles measured on controlled edges)
PHASE JITTER
AND
STATIC PHASE OFFSET
OUTPUT SKEW
nQ0:nQ4 80% Q0:Q4
80% VOD
tcycle
n
tcycle n+1
Clock Outputs
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
CYLE-TO-CYCLE JITTER
8745BY
20% tR tF
20%
OUTPUT RISE/FALL TIME
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REV. B DECEMBER 2, 2004
Integrated Circuit Systems, Inc.
ICS8745B
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
nCLK0, nCLK1 CLK0, CLK1 nQ0:nQ4 Q0:Q4
tPD
nQ0:nQ4 Q0:Q4
Pulse Width t
PERIOD
odc =
t PW t PERIOD
PROPAGATION DELAY
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDD out
VDD

DC Input
LVDS
out
out
VOS/ VOS
DC Input
LVDS
100
VOD/ VOD out
OFFSET VOLTAGE SETUP
DIFFERENTIAL OUTPUT VOLTAGE SETUP
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REV. B DECEMBER 2, 2004
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ICS8745B
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input
CLKx
V_REF
nCLKx
C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 2. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs.
3.3V 3.3V LVDS_Driv er + R1 100
-
100 Ohm Differiential Transmission Line
FIGURE 2. TYPICAL LVDS DRIVER TERMINATION
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ICS8745B
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8745B provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 3 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin.
3.3V VDD .01F VDDA .01F 10 F 10
FIGURE 3. POWER SUPPLY FILTERING
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 4A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 4B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 4C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
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BY
FIGURE 4D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
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REV. B DECEMBER 2, 2004
Integrated Circuit Systems, Inc.
ICS8745B
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
tem will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board.
LAYOUT GUIDELINE
The schematic of the ICS8745B layout example is shown in Figure 5A. The ICS8745B recommended PCB board layout for this example is shown in Figure 5B. This layout example is used as a general guideline. The layout in the actual sys-
VDD
SP = Space (i.e. not intstalled)
R7 RU2 SP RU3 1K RU4 1K RU5 SP RU6 1K RU7 SP CLK_SEL PLL_SEL SEL0 SEL1 SEL2 SEL3 PLL_SEL SEL3 VDDA 10 C11 0.01u C16 10u Zo = 50 Ohm + VDD
(77.76 MHz)
RD2 1K
RD3 SP
RD4 SP
RD5 1K
RD6 SP
RD7 1K
VDD
VDDO Zo = 50 Ohm
R4 100
-
LVDS_input
U3 3.3V
(155.5 MHz)
Zo = 50 Ohm SEL0 SEL1 1 2 3 4 5 6 7 8
VDD PLL_SEL VDDA SEL3 VDDO Q4 nQ4 GND
32 31 30 29 28 27 26 25
Zo = 50 Ohm CLK_SEL 3.3V PECL Driver R8A 50 R9 50
9 10 11 12 13 14 15 16
8745
VDD nFB_IN FB_IN SEL2 GND nQ0 Q0 VDDO
SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL MR
Q3 nQ3 VDDO Q2 nQ2 GND Q1 nQ1
24 23 22 21 20 19 18 17
VDD=3.3V VDDO=3.3V
SEL[3:0] = 0101, Divide by 2
R10 50
SEL2
R2 100
Decoupling capacitor located near the power pins
(U1-9) VDD
C1 0.1uF
(U1-32)
C6 0.1uF
(U1-22)
C4 0.1uF
VDDO
(U1-28)
C5 0.1uF
(U1-16)
C2 0.1uF
FIGURE 5A. ICS8745B LVDS ZERO DELAY BUFFER SCHEMATIC EXAMPLE
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The following component footprints are used in this layout example: All the resistors and capacitors are size 0603.
ICS8745B
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. * The differential 50 output traces should have same length. * Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. * Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. * To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. * Make sure no other signal traces are routed between the clock trace pair. * The matching termination resistors should be located as close to the receiver input pins as possible.
POWER
AND
GROUNDING
Place the decoupling capacitors C1, C6, C2, C4, and C5, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the VDDA pin as possible.
CLOCK TRACES
AND
TERMINATION
Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the
GND
R7 C16 C11 C5
VDDO
C6
U1
Pin 1
C4
VDD
VDDA
VIA
50 Ohm Traces
C1 C2
FIGURE 5B. PCB BOARD LAYOUT FOR ICS8745B
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REV. B DECEMBER 2, 2004
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ICS8745B
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8745B is: 2772
8745BY
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REV. B DECEMBER 2, 2004
Integrated Circuit Systems, Inc.
ICS8745B
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
32 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
8745BY
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REV. B DECEMBER 2, 2004
Integrated Circuit Systems, Inc.
ICS8745B
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Marking ICS8745BY ICS8745BY ICS8745BYLF ICS8745BYLF Package 32 Lead LQFP 32 Lead LQFP 32 Lead "Lead-Free" LQFP 32 Lead "Lead-Free" LQFP Shipping Packaging tray 1000 tape & reel tray 1000 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS8745BY ICS8745BYT ICS8745BYLF ICS8745BYLFT
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8745BY
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REV. B DECEMBER 2, 2004
Integrated Circuit Systems, Inc.
ICS8745B
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
REVISION HISTORY SHEET Description of Change LVDS DC Characteristics Table - modified VOS 0.90V min. to 1.05V min, 1.15V typical to 1.2V typical, and 1.4V max. to 1.35V max. Added Lead-Free bullet. Ordering Information Table - added Lead-Free par t. Features Section - delete bullet, "Industrial temperature available upon request." Ordering Information Table - added Lead-Free note. Date 3/17/04 12/2/04 3/18/05
Rev B B B
Table T4D T9
Page 5 1 14 1 14
T9
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